1. Field of the Invention
The present invention relates to an AD converter for converting an analog signal to a digital signal and a magnetic recording/regenerating apparatus using such AD converter.
2. Description of the Related Art
A high speed AD converter (hereinafter abbreviated to ADC) may be used for a regenerating circuit of a magnetic recording/regenerating apparatus using a constant density recording method. For an ADC used for a magnetic recording/regenerating apparatus of this method, it is necessary to convert data with a different frequency.
Constant density recording is necessary to effectively use a recording medium. For that purpose, as indicated in Japanese Patent Application Laid-Open No. 63-200306, there is a method available for changing the frequency for recording or regenerating according to the recording position. In this method, the magnetic recording density on the outer periphery is generally increased to almost the recording density on the inner periphery, so that the recording frequency for data on the outer periphery is increased.
An example showing an arrangement where an ADC is used for a regenerating circuit of a magnetic recording/regenerating apparatus is indicated in Japanese Patent Application Laid-Open No. 2-182032. The reason is that by converting and regenerating an analog signal on a recording medium corresponding to binary data coded by an RLL code such as (1, 7) code by an ADC, a high magnetic recording density can be obtained.
It is expected that a large capacity magnetic recording/regenerating apparatus can be obtained by using the above two methods together.
To convert and regenerate binary data by an ADC, generally a high speed ADC is necessary. Furthermore, when the method for changing the frequency of a magnetic disk unit for recording or regenerating is used together, the recording frequency for data on the outer periphery becomes high, so that a higher speed ADC is necessary. However, a higher speed ADC requires larger power consumption. Therefore, when a higher speed ADC is used as it is, the power consumption goes up and the recent need of low power consumption cannot be satisfied.
An art for changing the power consumption of an ADC in correspondence with a change in the conversion speed is indicated, for example, in Japanese Patent Application Laid-Open No. 62-204621. However, it is for a low speed integral-type ADC. In the case of a ramp (type) ADC, the conversion level is changed when the integral time is changed and a measure for it becomes an issue. For that purpose, changing the integral capacity of the integrator or changing the current of the constant current source so as to remove the charge from the integral capacity have been proposed. However, reducing the current of a high speed ADC which is not of the integral type has not been proposed.
There is a method for operating a plurality of ADCs in parallel available as an art for realizing a high speed ADC, which is indicated in Japanese Patent Application Laid-Open Nos. 60-183819, 3-70213, and 4-72919.
For the arts described in Japanese Patent Application Laid-Open Nos. 60-183819 and 4-72919 among them, reducing the power consumption is not described. For the art described in Japanese Patent Application Laid-Open No. 3-70213, an arrangement is only described for reduction of the power consumption that an ADC which is not to be used is turned off and no actual realization method is described.
Earlier filed patent applications of the present applicant and related to the present invention, include the Japanese Patent Application Laid-Open Nos. 3-205920 and 3-143116 (U.S. pending patent application Ser. No. 08/177,694) and the Japanese Patent Laid-Open No. 4-124456 (U.S. pending patent application Ser. No. 08/062,770). However, the former serves for operating a phase synchronizing circuit stably, but does not have means for directing a speed to the ADC and means for controlling an operating current for the comparator of the ADC.
The latter discloses means for accurately matching the delay time of a waveform equalizer with a period of the reproduced frequency, but does not have means for receiving the speed direction of the ADC and means for controlling an operating current for the comparator of the ADC.